4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR
نویسندگان
چکیده
This paper presents the simulation results of a 4ˆ4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 —m standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4ˆ4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
منابع مشابه
Low-Power 4×4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...
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